The invention relates to a switching arrangement for converting analog signals, more particularly pulse amplitude modulated (PAM) signals, into digital signals, more particularly pulse code modulated (PCM) signals, and for converting digital signals, more particularly PCM signals, into analog signals, more particularly PAM signals, by using an analog-to-digital converter operating in accordance with the iterative method.
Conventionally, converters for carrying out the foregoing functions use an analog comparator at one input of which there is located a storage capacitor to which is applied the analog signal to be converted into a digital signal and from the output of which a digital-to-analog converter is controlled by a register. The register receives, during the conversion of an analog signal into a digital signal, a continually changing code chain. During the conversion of a digital signal into an analog signal, the digital signal concerned is applied to the register. The digital-to-analog converter is connected by its output to the other input of the analog comparator.
A switching arrangement of the type described hereinabove, commonly referred to as a "codec" (coder/decoder), is known and is described in U.S. Pat. No. 3,883,864. In this prior art switching arrangement, an analog signal to be converted into a digital signal is stored as a PAM signal on a storage capacitor connected to an input of an analog comparator. To another input of the analog comparator, which is constituted by an operational amplifier, there is applied a reference voltage varying with time in accordance with a given characteristic. If the comparator in question finds an agreement between the signals being compared, it sends a drive pulse to a shift register in which with the occurrence of the drive pulse in question there is included a code chain which corresponds to the aforesaid analog signal. The code chain originates in a counter which with the occurrence of the reference voltage for the aforesaid analog comparator running through a given amplitude range sweeps through all the counter positions. Thus, there is a fixed relationship between the counter positions of the counter in question and the amplitudes of the reference voltage.
If a digital signal is to be converted into an analog signal with the switching arrangement described hereinabove, the digital signal is first compared by means of a digital comparator with the various code chains emitted from the aforesaid counter. If there is agreement between the digital signal and one of the code chains, a signal having the amplitude of the aforesaid comparator signal and existing at the time in question is buffered on another intermediate storage and passed on to a receiver over a separate circuit. Thus, two two-wire circuits are needed for the transmission of the analog signals: one two-wire circuit for the application of analog signals to be converted into digital signals, and another two-wire circuit for the retransmission of analog signals corresponding to converted digital signals. Thus, the number of circuits required is relatively great.
Another form of switching arrangement of the type mentioned hereinabove and also known as a codec is described in U.S. Pat. No. 3,540,037, wherein a digital signal to be converted into an analog signal, after storage in a register, controls an R-2R resistor network forming a digital-to-analog converter producing at the output of the resistor network an analog signal voltage corresponding to the digital signal being converted. The analog signal voltage is transmitted over a differential amplifier connected as an operational amplifier to a separate transmission line. An analog signal to be converted into a digital signal is applied to a comparator in conjunction with an analog reference voltage generated by the R-2R resistor network. In this case, the comparator controls, at its output, by means of a program control logic system, the setting or the contents of the register mentioned hereinabove which, in this case, functions as a counter and controls the R-2R resistor network.
If the comparator finds agreement between the analog signal applied thereto and the analog comparator voltage supplied by the R-2R resistor network, the setting of the register (counter) stops; the code chain existing in the register at the particular time then is the digital signal corresponding to the analog signal concerned and said digital signal can be transmitted over a separate circuit. Thus, in this prior art codec, too, two separate two-wire transmission circuits are necessary for the transmission of analog signals. As mentioned hereinabove, this requires a comparatively great number of circuits.
It is an object of the invention to provide a circuit arrangement of the type mentioned hereinabove capable of transmitting over one and the same two-wire circuit analog signals to be converted into digital signals and analog signals which are obtained by converting digital signals.